Modern multi-core processors have multiple pipelines to run multiple applications and as a result often improve performance for a system simultaneously running multiple tasks. Unfortunately, these multi-core processors also require substantially more power and use more area than a comparable single pipeline processor.
Prior art single pipeline processors may allow multi-thread processing by employing an operating system to manage hardware resource usage and thread switching. However, a significant performance penalty is incurred each time the processor changes threads, including context changes associated with interrupt handling. These processors generally include a single set of interrupt lines for providing interrupt requests to the processor, possibly leading to increased system inefficiency.